1. Field of the Invention
The present invention relates to a semiconductor device having a bonding pad. In particular, the present invention relates to a semiconductor device having a bonding pad and a test pad.
2. Description of the Related Art
For semiconductor chips, particularly for semiconductor chips which are required to have high reliability, tests of non-defective or defective chips are implemented to all the products in order to secure the reliability in recent years. Then, only the non-defective products are shipped. Such a test is generally carried out by using a “bonding pad” for connecting a peripheral region of a semiconductor chip with an external electrode. The bonding pad is electrically connected to the external electrode through a wire bonding, flip chip bonding and the like.
FIG. 1 is a cross-sectional view showing around a bonding pad of a conventional semiconductor chip having a multi-layer structure. A metal layer 31 is formed on a surface of the semiconductor chip. A cover layer 6 is formed to cover the metal layer 31. The cover layer 6 has an aperture through which the metal layer 31 is exposed. The metal layer 31 exposed in the aperture configures a bonding pad 10.
In addition, a metal layer 32 is provided below the metal layer 31 through an interlayer insulating layer. The metal layer 31 and the metal layer 32 are connected with a plurality of through holes 7 in order to prevent separation of the metal layer 31 at the testing time and the bonding time.
The metal layers 33, 34 and 35 are further formed under an area inner than the area where the bonding pad 10 is formed (in the left-side in FIG. 1). Thus, the semiconductor chip has a multi-layer structure. An internal circuit 4 such as an input/output circuit is formed by the metal layers and the like.
FIG. 2 shows a configuration around the bonding pad 10 more in detail. The bonding pad 10 is formed by the metal layer 31. At the bonding, an alloy layer 701 is formed on a bonding surface of a bonding ball 702. The bonding ball 702 is used for bonding the bonding pad 10 to a bonding wire material. When the bonding ball 702 is made of gold (Au) and the metal layer 31 is made of aluminum (Al), the alloy layer 701 is made of alloy of Au and Al in order to improve adhesion. In this case, aluminum contained in the metal layer 31 moves to the alloy layer 701 due to a high temperature process such as an annealing, which causes a void 703 to occur at the boundary between the alloy layer 701 and the metal layer 31 as shown in FIG. 2. The void 703 thus generated can cause deterioration of conjugate properties between the bonding ball 702 and the bonding pad 10.
In order to prevent the occurrence of the void 703, an Au layer 801 (or an Au layer and a barrier metal layer) can be formed on the surface of the metal layer 31 constituting the bonding pad 10, as shown in FIG. 3A. However, since the bonding pad 10 is used also for the testing as mentioned above, a test probe 802 is brought into contact with the Au layer 801 at the testing as shown in FIG. 3A. Here, the test probe 802 has needle-shape and is made of conductive material which is at least harder than Au. Therefore, gold scraped away from the Au layer 801 adheres to the needlepoint of the test probe 802 as shown in FIG. 3B. Thus, it is necessary to clean the needlepoint frequently to remove the attached gold, which reduces throughput. Moreover, the frequent cleaning abrades and thicken the needlepoint, which reduces life of the test probe 802. Furthermore, the AU adhered to the test probe 802 tends to reduce accuracy of the test.
Furthermore, even in the case when the Au layer 801 is provided, a stylus pressure of the test probe 802 at the measuring can cause a crack in the Au layer 801. In this case, aluminum of the metal layer 31 can move through the crack in the Au layer 801 and hence a void is generated. The void thus generated can cause deterioration of conjugate properties.
As described above, when the bonding pad 10 is shared in the bonding and in the testing, the test probe 802 is brought into contact with the bonding pad 10 as shown in FIG. 4A. In this case, the test probe 802 scratches the surface of the bonding pad 10 and hence the trace of the pad occurs. Moreover, when the test probe pressure is increased in order to ascertain the electric connection, not only the bonding pad 10 but also the plurality of through holes 7 formed below the metal layer 31 may be broken as shown in FIG. 4B. Therefore, according to the conventional technique as shown in FIG. 1, the internal circuit 4 can not be made under the bonding pad 10 in order to avoid the break of the internal circuit 4 at the time of the testing.
Also, the damage on the surface of the bonding pad 10 due to the contact of the test probe 802 deteriorates bonding strength of a wire bonding or a bump bonding which is formed in a packaging process. Particularly, in recent years, the pitch between the pads and the pad size decrease in accordance with the miniaturization of the semiconductor chip. For instance, a bonding pad 10 shown in FIG. 5 has the size of X=about 60 μm and Y=about 60 μm. The test probe can contact the bonding pad 10 in an area having the size of x=15-20 μm and y=30-50 μm as a contact area. When the area of the bonding pad 10 is sufficiently larger than the contact area, the bonding is secured by the other area than the contact area even if a bad connection occurs in the contact area. However, the area of the bonding pad 10 itself becomes small, the other area also becomes small. In this way, the miniaturizing of the bonding pad 10 causes insufficient bonding properties.
Moreover, as the pad size becomes small, the width of interconnection for electrically connecting the bonding pad 10 and the internal circuit becomes small. Since power supply ability is proportional to the width of the interconnection, the reduction of the width of the interconnection causes reduction of the power supply ability. In order to handle this problem, a bonding pad 10 may be formed with two metal layers which are connected with each other via through holes, and interconnections can be provided for both of the two metal layers in order to improve the power supply ability. However, such through holes can be destroyed due to the pressure of the test probe, which reduces the power supply ability of the lower metal layer.
As described above, according to the conventional technique, the head of the test probe is brought into contact with the bonding pad 10 in a wafer testing as the final of wafer processes, which results in the above-mentioned problems. That is to say, the bonding pad 10 being shared in the bonding and in the testing causes the above-mentioned problems.
Japanese Laid Open Patent Application (JP-P2002-329742) discloses a technique to solve these problems. According to this technique, a “test pad” is provided in addition to a “bonding pad” in order to prevent the occurrence of probe traces on the bonding pad at the time of the testing. That is, the bonding pad and the test pad are provided separately in order to improve the bonding properties of the bonding pad. In this case, however, it is necessary to reserve areas for both of the bonding pad and the test pad, which causes increase of the chip size and the cost.